Non-volatile memory cell and non-volatile cell array

A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. The first select transistor is connected with a source line and a first program word line. The first floating gate transistor has a first...

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Bibliographische Detailangaben
1. Verfasser:	Kuo, Ping-Yu
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CONTROLLING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS REGULATING SEMICONDUCTOR DEVICES STATIC STORES SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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Beschreibung
Zusammenfassung:	A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. The first select transistor is connected with a source line and a first program word line. The first floating gate transistor has a first floating gate. The first floating gate transistor is connected with the first select transistor and a first program bit line. The second select transistor is connected with the source line and a first read word line. The second floating gate transistor has a second floating gate. The second floating gate transistor is connected with the second select transistor and a first read bit line. The first floating gate and the second floating gate are connected with each other.