Electronic circuit configured to adjust sampling timing for recovering data

An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling cl...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Ryu, Kyungho, Pae, Hansu, Lim, Hyunwook, Lee, Kilhoon, Lee, Jaeyoul, Lim, Jung-Pil
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Ryu, Kyungho
Pae, Hansu
Lim, Hyunwook
Lee, Kilhoon
Lee, Jaeyoul
Lim, Jung-Pil
description An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10763866B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10763866B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10763866B23</originalsourceid><addsrcrecordid>eNqNykEKwjAQQNFuXIh6h_EAglqIXSsVwaW6LsNkUiJpJiQTzy8FD-Dq8eEvm3sfmDRL9ATkM1WvQBKdH2tmCyqA9l2LQsEpBR9HUD_NOMmQmeTDeU6Liutm4TAU3vxcNdtr_7zcdpxk4JKQOLIOr8dhfzJtZ8z52P7zfAGfTDYX</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Electronic circuit configured to adjust sampling timing for recovering data</title><source>esp@cenet</source><creator>Ryu, Kyungho ; Pae, Hansu ; Lim, Hyunwook ; Lee, Kilhoon ; Lee, Jaeyoul ; Lim, Jung-Pil</creator><creatorcontrib>Ryu, Kyungho ; Pae, Hansu ; Lim, Hyunwook ; Lee, Kilhoon ; Lee, Jaeyoul ; Lim, Jung-Pil</creatorcontrib><description>An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200901&amp;DB=EPODOC&amp;CC=US&amp;NR=10763866B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200901&amp;DB=EPODOC&amp;CC=US&amp;NR=10763866B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ryu, Kyungho</creatorcontrib><creatorcontrib>Pae, Hansu</creatorcontrib><creatorcontrib>Lim, Hyunwook</creatorcontrib><creatorcontrib>Lee, Kilhoon</creatorcontrib><creatorcontrib>Lee, Jaeyoul</creatorcontrib><creatorcontrib>Lim, Jung-Pil</creatorcontrib><title>Electronic circuit configured to adjust sampling timing for recovering data</title><description>An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNykEKwjAQQNFuXIh6h_EAglqIXSsVwaW6LsNkUiJpJiQTzy8FD-Dq8eEvm3sfmDRL9ATkM1WvQBKdH2tmCyqA9l2LQsEpBR9HUD_NOMmQmeTDeU6Liutm4TAU3vxcNdtr_7zcdpxk4JKQOLIOr8dhfzJtZ8z52P7zfAGfTDYX</recordid><startdate>20200901</startdate><enddate>20200901</enddate><creator>Ryu, Kyungho</creator><creator>Pae, Hansu</creator><creator>Lim, Hyunwook</creator><creator>Lee, Kilhoon</creator><creator>Lee, Jaeyoul</creator><creator>Lim, Jung-Pil</creator><scope>EVB</scope></search><sort><creationdate>20200901</creationdate><title>Electronic circuit configured to adjust sampling timing for recovering data</title><author>Ryu, Kyungho ; Pae, Hansu ; Lim, Hyunwook ; Lee, Kilhoon ; Lee, Jaeyoul ; Lim, Jung-Pil</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10763866B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Ryu, Kyungho</creatorcontrib><creatorcontrib>Pae, Hansu</creatorcontrib><creatorcontrib>Lim, Hyunwook</creatorcontrib><creatorcontrib>Lee, Kilhoon</creatorcontrib><creatorcontrib>Lee, Jaeyoul</creatorcontrib><creatorcontrib>Lim, Jung-Pil</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ryu, Kyungho</au><au>Pae, Hansu</au><au>Lim, Hyunwook</au><au>Lee, Kilhoon</au><au>Lee, Jaeyoul</au><au>Lim, Jung-Pil</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Electronic circuit configured to adjust sampling timing for recovering data</title><date>2020-09-01</date><risdate>2020</risdate><abstract>An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US10763866B2
source esp@cenet
subjects AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
title Electronic circuit configured to adjust sampling timing for recovering data
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T10%3A26%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ryu,%20Kyungho&rft.date=2020-09-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10763866B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true