Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers

An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad....

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Jack, Nathan D, Gauthier, Jr., Robert J, Mitra, Souvick, Di Sarro, James P, Li, JunJun
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING CONVERSION OR DISTRIBUTION OF ELECTRIC POWER COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS GENERATION PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.