System, method and computer program product for accelerating iterative graph algorithms by memory layout optimization

System, method and computer program product for accelerating iterative graph algorithms by memory layout optimization

An iterative graph algorithm accelerating method, system, and computer program product, include recording an order of access nodes in a memory layout, reordering the access nodes in the memory layout in accordance with the recorded order, and updating edge information of the reordered access nodes.

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Bibliographische Detailangaben
Hauptverfasser: Finkler, Ulrich Alfons, Cho, Minsik, Kung, David Shing-ki, Brand, Daniel, Puri, Ruchir
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:An iterative graph algorithm accelerating method, system, and computer program product, include recording an order of access nodes in a memory layout, reordering the access nodes in the memory layout in accordance with the recorded order, and updating edge information of the reordered access nodes.