Deuterium-based passivation of non-planar transistor interfaces

Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.