No miss cache structure for real-time image transformations with multiple LSR processing engines

Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input ima...

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Bibliographische Detailangaben
Hauptverfasser:	Bradford, Jeffrey Powers, Johnson, Christopher Jon, Haraden, Ryan Scott, Muff, Adam James, Leung, Gene, Comparan, Miguel, Ozguner, Tolga
Format:	Patent
Sprache:	eng
Schlagworte:	ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CALCULATING COMPUTING COUNTING CRYPTOGRAPHY DISPLAY EDUCATION ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS OPTICS PHYSICS SEALS
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Beschreibung
Zusammenfassung:	Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.