Power monitoring calibration to a target performance level
Systems and methods for performing power monitoring calibration to a target performance level are described. In some embodiments, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a logic circuit coupled to the plurality of CPUs, the logic circuit co...
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| creator | Khatri, Mukund P Jenne, John Erven |
| description | Systems and methods for performing power monitoring calibration to a target performance level are described. In some embodiments, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a logic circuit coupled to the plurality of CPUs, the logic circuit configured to: measure an operating performance level for each of the plurality of CPUs under a controlled workload and, in response to a determination that the operating performance level of any given one of the CPUs does not match a target performance level for all of the CPUs, apply an offset to a voltage regulator measurement associated with the given CPU that causes the operating performance level of the given CPU to match the target performance level for all of the CPUs. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10635146B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10635146B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10635146B23</originalsourceid><addsrcrecordid>eNrjZLAKyC9PLVLIzc_LLMkvysxLV0hOzMlMKkosyczPUyjJV0hUKEksSk8tUShILUrLL8pNzEtOVchJLUvN4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgZmxqaGJmZORsbEqAEAoL8veQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Power monitoring calibration to a target performance level</title><source>esp@cenet</source><creator>Khatri, Mukund P ; Jenne, John Erven</creator><creatorcontrib>Khatri, Mukund P ; Jenne, John Erven</creatorcontrib><description>Systems and methods for performing power monitoring calibration to a target performance level are described. In some embodiments, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a logic circuit coupled to the plurality of CPUs, the logic circuit configured to: measure an operating performance level for each of the plurality of CPUs under a controlled workload and, in response to a determination that the operating performance level of any given one of the CPUs does not match a target performance level for all of the CPUs, apply an offset to a voltage regulator measurement associated with the given CPU that causes the operating performance level of the given CPU to match the target performance level for all of the CPUs.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200428&DB=EPODOC&CC=US&NR=10635146B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200428&DB=EPODOC&CC=US&NR=10635146B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Khatri, Mukund P</creatorcontrib><creatorcontrib>Jenne, John Erven</creatorcontrib><title>Power monitoring calibration to a target performance level</title><description>Systems and methods for performing power monitoring calibration to a target performance level are described. In some embodiments, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a logic circuit coupled to the plurality of CPUs, the logic circuit configured to: measure an operating performance level for each of the plurality of CPUs under a controlled workload and, in response to a determination that the operating performance level of any given one of the CPUs does not match a target performance level for all of the CPUs, apply an offset to a voltage regulator measurement associated with the given CPU that causes the operating performance level of the given CPU to match the target performance level for all of the CPUs.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAKyC9PLVLIzc_LLMkvysxLV0hOzMlMKkosyczPUyjJV0hUKEksSk8tUShILUrLL8pNzEtOVchJLUvN4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgZmxqaGJmZORsbEqAEAoL8veQ</recordid><startdate>20200428</startdate><enddate>20200428</enddate><creator>Khatri, Mukund P</creator><creator>Jenne, John Erven</creator><scope>EVB</scope></search><sort><creationdate>20200428</creationdate><title>Power monitoring calibration to a target performance level</title><author>Khatri, Mukund P ; Jenne, John Erven</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10635146B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Khatri, Mukund P</creatorcontrib><creatorcontrib>Jenne, John Erven</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Khatri, Mukund P</au><au>Jenne, John Erven</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Power monitoring calibration to a target performance level</title><date>2020-04-28</date><risdate>2020</risdate><abstract>Systems and methods for performing power monitoring calibration to a target performance level are described. In some embodiments, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a logic circuit coupled to the plurality of CPUs, the logic circuit configured to: measure an operating performance level for each of the plurality of CPUs under a controlled workload and, in response to a determination that the operating performance level of any given one of the CPUs does not match a target performance level for all of the CPUs, apply an offset to a voltage regulator measurement associated with the given CPU that causes the operating performance level of the given CPU to match the target performance level for all of the CPUs.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Power monitoring calibration to a target performance level |
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