Power monitoring calibration to a target performance level

Systems and methods for performing power monitoring calibration to a target performance level are described. In some embodiments, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a logic circuit coupled to the plurality of CPUs, the logic circuit configured to: measure an operating performance level for each of the plurality of CPUs under a controlled workload and, in response to a determination that the operating performance level of any given one of the CPUs does not match a target performance level for all of the CPUs, apply an offset to a voltage regulator measurement associated with the given CPU that causes the operating performance level of the given CPU to match the target performance level for all of the CPUs.