Low-power and low-latency distortion correction for image processors

An image processing system incorporates a distortion correction (DC) sub-system in order to quickly correct skewed images. The DC sub-system includes a buffer, a processor and a sparse matrix table (SMT). The buffer is sized according to an amount of distortion in an input image. Input image pixels from an input frame are buffered in the buffer, and other input image pixels from the same frame overwrite the buffered input image pixels, reducing latency of the DC sub-system. The SMT is dynamically configurable and provides mapping values for mapping output pixels to input pixels. The processor implements combinational logic, including multipliers, lookup tables and adders. The combinational logic interpolates flow control parameters, pixel coordinate values, and pixel intensity values. The distortion correction values are streamed to a display or provided to a subsequent image processing block for further processing.