Dynamic gate drive system and control method

A switching circuit includes a semiconductor switch having a Gate terminal, and includes first, second, third, and fourth Gate resistors. The Gate resistors have upstream and downstream ends relative to a location of the semiconductor switch or a driven load. The downstream ends connect to the Gate terminal. First, second, third, and fourth buffer switches have Gate terminals and Source terminals, with the Source terminals connected to the upstream ends of the first, second, third, and fourth Gate resistors, respectively. An optional Gate driver integrated circuit (IC) connects to the Gate terminals of the buffer switches. A microcontroller, responsive to circuit measurements, selects switching control values and Gate resistor identities based on the measurements, and transmits switching control signals and a Gate resistor selection signal to select on/off states of the buffer switches and an optimum switching speed for the semiconductor switch.