Application specific instruction-set processor (ASIP) architecture having separated input and output data ports

The invention provide an application specific instruction-set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for executing atomic application specific instructions. The ASIP includes one or more units for executing a first set of atomic application specific instructions for receiving a first set of data across a plurality of input data ports in a first operation specified in an instruction word. Further, the one or more units execute a second set of atomic application specific instructions for outputting a second set of data across a plurality of output data ports in a second operation specified in the instruction word, wherein an input data port of the plurality of input data ports and a corresponding output data port of the plurality of output data ports share a same address location and are specified as operands in the instruction word. Thus, the first operation and the second operation can occur simultaneously.