Coupling aware wire capacitance adjust at global routing

A system for semiconductor chip fabrication. A host system hosts a capacitance adjust tool for performing calculating a ground capacitance adjust for a wire segment going through routing tiles according to the following operations; providing the routing tiles having a plurality of wires wherein the wire segment being a victim wire and neighboring wires being aggressor wires; computing ground capacitance adjusts for a victim wire averaged across all aggressor slew values and across possible spacing values between the victim wire and the neighboring aggressor wires to take into account a potential coupling effect by the neighboring aggressor wires, to guide placement of the wire segment in the routing tiles to avoid coupling noise; and outputting the placement of the wire segments to a tool for manufacturing the semiconductor chip.