Fast settling peak detector

The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in t...

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Bibliographische Detailangaben
1. Verfasser:	Karmaker, Rahul
Format:	Patent
Sprache:	eng
Schlagworte:	AMPLIFIERS BASIC ELECTRONIC CIRCUITRY CONTROL OF AMPLIFICATION CONTROLLING ELECTRICITY INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE REGULATING STATIC STORES SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES TESTING
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Beschreibung
Zusammenfassung:	The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.