Controlling a performance state of a processor using a combination of package and thread hint information

Controlling a performance state of a processor using a combination of package and thread hint information

In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one o...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Rajwan, Doron, Weissmann, Eliezer, Ananthakrishnan, Avinash N, Melamed, Ido, Rotem, Efraim, Therien, Guy M, Hirsh, Israel, Abitan, Natanel
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.