Different scaling ratio in FEOL/ MOL/ BEOL

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A plurality of first MOL (middle-of-line) structures are arranged at a first pitch over the substrate at locations interleaved between the plur...

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Bibliographische Detailangaben
Hauptverfasser:	Lee, Liang-Yao, Tsai, Tsung-Chieh, Wu, Juing-Yi, Lee, Chun-Yi
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A plurality of first MOL (middle-of-line) structures are arranged at a first pitch over the substrate at locations interleaved between the plurality of gate structures. The plurality of first MOL structures connect active regions within the substrate to an overlying metal interconnect layer. A plurality of second MOL structures are arranged at a second pitch over the plurality of gate structures at locations interleaved between the plurality of first MOL structures. The plurality of second MOL structures connect the plurality of gate structures to the metal interconnect layer. The second pitch is different than the first pitch. The different pitches avoid misalignment errors between the plurality of gate structures and the metal interconnect layer.