Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer

A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse...

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Hauptverfasser: Bajaj, Mohit, Hook, Terence B, Sathiyanarayanan, Rajesh, Ando, Takashi, Pandey, Rajan K
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creator Bajaj, Mohit
Hook, Terence B
Sathiyanarayanan, Rajesh
Ando, Takashi
Pandey, Rajan K
description A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10319596B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10319596B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10319596B23</originalsourceid><addsrcrecordid>eNqNyksKwjAUheFOHIi6h-sCCtai0KkvnKvjcm1Pk2CalOS2xd1bwQUIB34OfPPkecJgKkQajWhqeyumsyDRAVF7W9PgrbCaQONDi5q8I6ZonJrUyA0C9d9HUQIbR9NEg7RROn2R5TfCMpk1bCNWvy6S9eV8P15TdL5E7LiCg5SPW7bJs2JX7A_b_B_zAUfXPfQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer</title><source>esp@cenet</source><creator>Bajaj, Mohit ; Hook, Terence B ; Sathiyanarayanan, Rajesh ; Ando, Takashi ; Pandey, Rajan K</creator><creatorcontrib>Bajaj, Mohit ; Hook, Terence B ; Sathiyanarayanan, Rajesh ; Ando, Takashi ; Pandey, Rajan K</creatorcontrib><description>A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190611&amp;DB=EPODOC&amp;CC=US&amp;NR=10319596B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190611&amp;DB=EPODOC&amp;CC=US&amp;NR=10319596B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Bajaj, Mohit</creatorcontrib><creatorcontrib>Hook, Terence B</creatorcontrib><creatorcontrib>Sathiyanarayanan, Rajesh</creatorcontrib><creatorcontrib>Ando, Takashi</creatorcontrib><creatorcontrib>Pandey, Rajan K</creatorcontrib><title>Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer</title><description>A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyksKwjAUheFOHIi6h-sCCtai0KkvnKvjcm1Pk2CalOS2xd1bwQUIB34OfPPkecJgKkQajWhqeyumsyDRAVF7W9PgrbCaQONDi5q8I6ZonJrUyA0C9d9HUQIbR9NEg7RROn2R5TfCMpk1bCNWvy6S9eV8P15TdL5E7LiCg5SPW7bJs2JX7A_b_B_zAUfXPfQ</recordid><startdate>20190611</startdate><enddate>20190611</enddate><creator>Bajaj, Mohit</creator><creator>Hook, Terence B</creator><creator>Sathiyanarayanan, Rajesh</creator><creator>Ando, Takashi</creator><creator>Pandey, Rajan K</creator><scope>EVB</scope></search><sort><creationdate>20190611</creationdate><title>Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer</title><author>Bajaj, Mohit ; Hook, Terence B ; Sathiyanarayanan, Rajesh ; Ando, Takashi ; Pandey, Rajan K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10319596B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Bajaj, Mohit</creatorcontrib><creatorcontrib>Hook, Terence B</creatorcontrib><creatorcontrib>Sathiyanarayanan, Rajesh</creatorcontrib><creatorcontrib>Ando, Takashi</creatorcontrib><creatorcontrib>Pandey, Rajan K</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bajaj, Mohit</au><au>Hook, Terence B</au><au>Sathiyanarayanan, Rajesh</au><au>Ando, Takashi</au><au>Pandey, Rajan K</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer</title><date>2019-06-11</date><risdate>2019</risdate><abstract>A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T00%3A41%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Bajaj,%20Mohit&rft.date=2019-06-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10319596B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true