Maintaining slew rate while loading flash memory dies

Systems and methods for maintaining a slew rate while loading flash memory dies are described. In one embodiment, the systems and methods may include placing one or more comparator circuits connectively between one or more channel controllers and a plurality of flash memory dies and maintaining a sl...

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Bibliographische Detailangaben
Hauptverfasser:	Laguvaram, Abhishek, Huddar, Vinod Arjun
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES
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Beschreibung
Zusammenfassung:	Systems and methods for maintaining a slew rate while loading flash memory dies are described. In one embodiment, the systems and methods may include placing one or more comparator circuits connectively between one or more channel controllers and a plurality of flash memory dies and maintaining a slew rate in relation to the one or more channel controllers writing data to a plurality of flash memory dies inside the solid state drive. In some cases, a hardware controller of a solid state drive may include the one or more channel controllers. In some cases, the plurality of flash memory dies may include at least one NAND die.