Support apparatus and method for processing data and using hardware support for atomic memory transactions

An asymmetric multiprocessor system includes a plurality of processor cores supporting transactional memory via controllers as well as one or more processor cores which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processors is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processor is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processor is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times. The request may arise through execution of a transaction start instruction which serves to read a lock address from an architectural register storing the lock address should the processor executing that transaction start instruction not already be executing a pending memory transaction. If the processor is already executing a memory transaction, then the transaction start instruction need not access the lock value stored at the lock address held within the lock address register as it may be assumed that the lock value has already been checked.