System and method for address-mapped control of field programmable gate array (FPGA) via ethernet

A method includes receiving, at a field programmable gate array (FPGA), one or more Ethernet packets of a message including control or status information associated with the FPGA. The method also includes determining, by the FPGA, a payload of each packet by removing at least one Ethernet header from the packet. The method further includes removing, by the FPGA, a User Datagram Protocol (UDP) header from each packet and determining UDP header metadata. The method also includes converting, by the FPGA based on the UDP header metadata, the packets to a read or write message associated with one or more registers of the FPGA. In addition, the method includes performing, by the FPGA, a read or write of the one or more registers of the FPGA according to the read or write message.