Self-timed processors implemented with multi-rail null convention logic and unate gates

There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of...

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Hauptverfasser: Cope, Bryan Garnett, Raghavan, Gopal, Havlicek, John Whitaker, Wijayasekara, Vidura Manu, Xu, Chao, Baker, David Cureton, Melton, Ben Wiley
Format: Patent
Sprache:eng
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Zusammenfassung:There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.