Method of estimating a yield of an integrated circuit and method of optimizing a design for an integrated circuit
Methods of estimating yields of integrated circuits and methods of optimizing designs for the integrated circuits are provided. In a method of estimating a yield of an integrated circuit, critical paths are extracted from timing paths included in the integrated circuit by performing a static timing...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | Methods of estimating yields of integrated circuits and methods of optimizing designs for the integrated circuits are provided. In a method of estimating a yield of an integrated circuit, critical paths are extracted from timing paths included in the integrated circuit by performing a static timing analysis for the integrated circuit. The critical paths are grouped into criticality sigma level groups according to criticality sigma levels of the critical paths, and the yield of the integrated circuit is determined based on numbers of the critical paths belonging to the respective criticality sigma level groups. |
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