Downstream device service latency reporting for power management

An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the e...

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Bibliographische Detailangaben
Hauptverfasser:	Walsh, Jim, Cooper, Barnes, Jeyaseelan, Jaya L, Songer, Neil W, Gough, Robert E
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS PHYSICS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION WIRELESS COMMUNICATIONS NETWORKS
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Beschreibung
Zusammenfassung:	An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.