Method and system for resetting processors of a gateway device
A system includes a first processor and a second processor coupled to the first processor through a high speed connection and a low speed connection. The first processor and the second processor are disposed within a first device. The first processor and the second processor exchange heartbeat signa...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A system includes a first processor and a second processor coupled to the first processor through a high speed connection and a low speed connection. The first processor and the second processor are disposed within a first device. The first processor and the second processor exchange heartbeat signals therebetween through the low speed connection. The first processor communicates a first reset signal through a reset line to the second processor when the first processor does not receive a first heartbeat signal of the heartbeat signals from the second processor. The second processor resets in response to the first reset signal. |
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