VLIW type instruction packet structure and processor suitable for processing such an instruction packet
A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multi...
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| Zusammenfassung: | A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable. |
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