Apparatus and method to force equivalent outputs at start-up for replicated sequential circuits

A method and apparatus for forcing equivalent outputs at start-up for replicated sequential circuits is disclosed. An integrated circuit (IC) includes first and second clocked logic circuits each coupled to receive a clock signal common to both, and each configured to produce equivalent logical outputs based on a common set of logic inputs. The IC further includes an equivalence circuit coupled to the outputs of each of the first and second clocked logic circuits. During a system start-up (e.g., power on) and before the clock signal has been applied, the equivalence circuit may detect if the outputs of the to first and second clocked logic circuits originally come up in different states. Responsive to determining that the outputs of the first and second clocked logic circuits are different, the equivalence circuit may cause the outputs to be forced to the same logical state.