Circuit layouts of tamper-respondent sensors

Tamper-respondent assemblies and methods of fabrication are provided which include a tamper-respondent electronic circuit structure. The tamper-respondent electronic circuit structure includes, for instance, a tamper-respondent sensor having at least one flexible layer and paired conductive lines disposed on the at least one flexible layer. The paired conductive lines form, at least in part, at least one tamper-detect network of the tamper-respondent sensor. The tamper-respondent electronic circuit structure further includes monitor circuitry electrically connected to the paired conductive lines to differentially monitor the paired conductive lines for a tamper event. In enhanced embodiments, multiple interconnect vias electrically connect to two or more layers of paired conductive lines and are disposed in an unfolded interconnect area of the tamper-respondent sensor when the sensor is operatively positioned about an electronic component or assembly to be protected.