Methods and devices for reducing clock skew in bidirectional clock trees

The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and the branch includes a tunable delay buffer that operates to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.