Techniques for data retention in memory cells during power interruption

Volatile memory is described, comprising: (i) a first inverter comprising a first p-type field effect transistor (FET) connected to a first n-type FET; (ii) a second inverter comprising a second p-type FET connected to a second n-type FET; (iii) a third p-type FET; (iv) a fourth p-type FET; and (v)...

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Bibliographische Detailangaben
1. Verfasser:	Liran, Tuvia
Format:	Patent
Sprache:	eng
Schlagworte:	BANDAGES, DRESSINGS OR ABSORBENT PADS DEVICES PROVIDING PATENCY TO, OR PREVENTING COLLAPSING OF,TUBULAR STRUCTURES OF THE BODY, E.G. STENTS ELECTRICITY ELECTROTHERAPY FILTERS IMPLANTABLE INTO BLOOD VESSELS FIRST-AID KITS FOMENTATION HUMAN NECESSITIES HYGIENE INFORMATION STORAGE MAGNETOTHERAPY MEDICAL OR VETERINARY SCIENCE ORTHOPAEDIC, NURSING OR CONTRACEPTIVE DEVICES PHYSICS PROSTHESES RADIATION THERAPY STATIC STORES TREATMENT OR PROTECTION OF EYES OR EARS ULTRASOUND THERAPY
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Beschreibung
Zusammenfassung:	Volatile memory is described, comprising: (i) a first inverter comprising a first p-type field effect transistor (FET) connected to a first n-type FET; (ii) a second inverter comprising a second p-type FET connected to a second n-type FET; (iii) a third p-type FET; (iv) a fourth p-type FET; and (v) a floating line connecting (i) a source of the third p-type FET, and (ii) a source of the fourth p-type FET, wherein: (a) the first data line is connected to: a gate of the second p-type FET, a gate of the second n-type FET, a drain of the third p-type FET, and a gate of the fourth p-type FET, and (b) the second data line is connected to: a gate of the first p-type FET, a gate of the first n-type FET, a drain of the fourth p-type FET, and a gate of the third p-type FET.