Context switching mechanism for a processor having a general purpose core and a tightly coupled accelerator

In one embodiment, a processor includes an accelerator, a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction, and an execution unit to execute the first decoded instruction to, for a thread executing on the accelerator that is to be placed in an inactive state, cause a save of context information for the thread, and a save of a vector identifying the accelerator corresponding to the context information, and execute the second decoded instruction to read the vector to determine the accelerator to restore saved context information into for the thread, read the saved context information, and restore the saved context information into the accelerator.