Integrated circuit packaging system with substrate and method of manufacture thereof

An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a con...

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Hauptverfasser: Foh, Bartholomew Liao Chung, Lee, Soo Won, Punzalan, Jeffrey David, Chai, SeungYong, Szeto, Kwok Keung, Do, Byung Tai, Kim, KyungOe, Kim, Kyung Moon, Cuong, Dao Nguyen Phu
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creator Foh, Bartholomew Liao Chung
Lee, Soo Won
Punzalan, Jeffrey David
Chai, SeungYong
Szeto, Kwok Keung
Do, Byung Tai
Kim, KyungOe
Kim, Kyung Moon
Cuong, Dao Nguyen Phu
description An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10109587B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10109587B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10109587B13</originalsourceid><addsrcrecordid>eNqNzD0KAjEQQOE0FqLeYTyAsEFEbRVFa9d6GbOTHzTJkpkg3l4FD2D1mo83Vu05CbmCQj2YUEwNAgOaO7qQHPCLhSI8g3jgemP5QsDUQyTxuYdsIWKqFo3UQiCeCmU7VSOLD6bZrxM1Px7a_WlBQ-6IP39KJN31ohvdbFeb9U4v_zFv8VE5mQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit packaging system with substrate and method of manufacture thereof</title><source>esp@cenet</source><creator>Foh, Bartholomew Liao Chung ; Lee, Soo Won ; Punzalan, Jeffrey David ; Chai, SeungYong ; Szeto, Kwok Keung ; Do, Byung Tai ; Kim, KyungOe ; Kim, Kyung Moon ; Cuong, Dao Nguyen Phu</creator><creatorcontrib>Foh, Bartholomew Liao Chung ; Lee, Soo Won ; Punzalan, Jeffrey David ; Chai, SeungYong ; Szeto, Kwok Keung ; Do, Byung Tai ; Kim, KyungOe ; Kim, Kyung Moon ; Cuong, Dao Nguyen Phu</creatorcontrib><description>An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20181023&amp;DB=EPODOC&amp;CC=US&amp;NR=10109587B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20181023&amp;DB=EPODOC&amp;CC=US&amp;NR=10109587B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Foh, Bartholomew Liao Chung</creatorcontrib><creatorcontrib>Lee, Soo Won</creatorcontrib><creatorcontrib>Punzalan, Jeffrey David</creatorcontrib><creatorcontrib>Chai, SeungYong</creatorcontrib><creatorcontrib>Szeto, Kwok Keung</creatorcontrib><creatorcontrib>Do, Byung Tai</creatorcontrib><creatorcontrib>Kim, KyungOe</creatorcontrib><creatorcontrib>Kim, Kyung Moon</creatorcontrib><creatorcontrib>Cuong, Dao Nguyen Phu</creatorcontrib><title>Integrated circuit packaging system with substrate and method of manufacture thereof</title><description>An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzD0KAjEQQOE0FqLeYTyAsEFEbRVFa9d6GbOTHzTJkpkg3l4FD2D1mo83Vu05CbmCQj2YUEwNAgOaO7qQHPCLhSI8g3jgemP5QsDUQyTxuYdsIWKqFo3UQiCeCmU7VSOLD6bZrxM1Px7a_WlBQ-6IP39KJN31ohvdbFeb9U4v_zFv8VE5mQ</recordid><startdate>20181023</startdate><enddate>20181023</enddate><creator>Foh, Bartholomew Liao Chung</creator><creator>Lee, Soo Won</creator><creator>Punzalan, Jeffrey David</creator><creator>Chai, SeungYong</creator><creator>Szeto, Kwok Keung</creator><creator>Do, Byung Tai</creator><creator>Kim, KyungOe</creator><creator>Kim, Kyung Moon</creator><creator>Cuong, Dao Nguyen Phu</creator><scope>EVB</scope></search><sort><creationdate>20181023</creationdate><title>Integrated circuit packaging system with substrate and method of manufacture thereof</title><author>Foh, Bartholomew Liao Chung ; Lee, Soo Won ; Punzalan, Jeffrey David ; Chai, SeungYong ; Szeto, Kwok Keung ; Do, Byung Tai ; Kim, KyungOe ; Kim, Kyung Moon ; Cuong, Dao Nguyen Phu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10109587B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Foh, Bartholomew Liao Chung</creatorcontrib><creatorcontrib>Lee, Soo Won</creatorcontrib><creatorcontrib>Punzalan, Jeffrey David</creatorcontrib><creatorcontrib>Chai, SeungYong</creatorcontrib><creatorcontrib>Szeto, Kwok Keung</creatorcontrib><creatorcontrib>Do, Byung Tai</creatorcontrib><creatorcontrib>Kim, KyungOe</creatorcontrib><creatorcontrib>Kim, Kyung Moon</creatorcontrib><creatorcontrib>Cuong, Dao Nguyen Phu</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Foh, Bartholomew Liao Chung</au><au>Lee, Soo Won</au><au>Punzalan, Jeffrey David</au><au>Chai, SeungYong</au><au>Szeto, Kwok Keung</au><au>Do, Byung Tai</au><au>Kim, KyungOe</au><au>Kim, Kyung Moon</au><au>Cuong, Dao Nguyen Phu</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit packaging system with substrate and method of manufacture thereof</title><date>2018-10-23</date><risdate>2018</risdate><abstract>An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Integrated circuit packaging system with substrate and method of manufacture thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-19T11%3A56%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Foh,%20Bartholomew%20Liao%20Chung&rft.date=2018-10-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10109587B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true