Automated checker generation

The invention relates to a method for verifying a design of an electronic circuit. The electronic circuit comprises at least one register including one or more parts. After receiving specification information of said register, a register monitor module is automatically created based on said received specification information. The register monitor module comprises a scoreboard for each part of the register. Said scoreboard comprises an expected data value queue for receiving expected data values, an actual data value queue for receiving actual data values. Furthermore, the register monitor module provides a matching strategy for comparing expected data values with actual data values. Expected data values and actual data values are compared for each scoreboard based on the matching strategy and an error indication is generated if the result of the comparison step does not fulfill the requirements specified in the matching strategy.