Integrated circuits having an anti-fuse device and methods of forming the same

Integrated circuits and methods of forming the same are provided. An exemplary integrated circuit includes a semiconductor substrate and an anti-fuse device having a select transistor, a bitline contact, and a split channel transistor. The select transistor includes a select gate structure, a bitline source/drain region, and a shared source/drain region. The bitline contact is disposed over and in electrical communication with the bitline source/drain region. The split channel transistor is in electrical communication with the select transistor through the shared source/drain region. The split channel transistor includes an anti-fuse gate structure having an anti-fuse gate and an anti-fuse dielectric layer and a stepped gate structure disposed between the anti-fuse gate structure and the shared source/drain region and having a stepped gate and a stepped dielectric layer. The stepped dielectric layer has a greater thickness than the anti-fuse dielectric layer.