Memory and memory control method

A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Maeda, Masazumi, Ise, Masahiro
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until an amount of electric charges stored in the electric charge storage layer decreases to an amount of electric charges corresponding to a state where the data is erased from the memory cell.