METHOD FOR FORMATION OF ARSENIDE-GALLIUM HETERO-EPITAXIAL STRUCTURES FOR SUBMICRON SHF-LARGE INTEGRATED CIRCUITS

METHOD FOR FORMATION OF ARSENIDE-GALLIUM HETERO-EPITAXIAL STRUCTURES FOR SUBMICRON SHF-LARGE INTEGRATED CIRCUITS

A method for formation of arsenide-gallium hetero-epitaxial structures for submicron SHF-large integrated circuit, which comprises KEF 0,1 (111) silicon substrates preparation, which have surface 3-4 °, chemical treatment thereof in Caro etchant to clean surface. A process for deposition of n-layers...

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Hauptverfasser: VARVARUK VASYL MYKOLAIOVYCH, KINDRAT TARAS PETROVYCH, NOVOSIADLYI STEPAN PETROVYCH, MELNYK LIUBOMYR VASYLIOVYCH
Format: Patent
Sprache:eng ; rus ; ukr
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:A method for formation of arsenide-gallium hetero-epitaxial structures for submicron SHF-large integrated circuit, which comprises KEF 0,1 (111) silicon substrates preparation, which have surface 3-4 °, chemical treatment thereof in Caro etchant to clean surface. A process for deposition of n-layers GaAs is realized by low-temperature plasma epitaxial (T