Substrate and simecondutor device

Substrate and simecondutor device

A board-level pad pattern includes a printed circuit board, PCB, substrate; an exposed pad region (30) disposed within a surface mount region (10) of the base substrate; and multiple staggered ball pads disposed within the surface mount region (10) arranged in a ring shape around the exposed pad reg...

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Hauptverfasser: TANG, HUII, HO, SHAOUN, LIN, HSUAN-YI, HUANG, PU-SHAN
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator TANG, HUII
HO, SHAOUN
LIN, HSUAN-YI
HUANG, PU-SHAN
description A board-level pad pattern includes a printed circuit board, PCB, substrate; an exposed pad region (30) disposed within a surface mount region (10) of the base substrate; and multiple staggered ball pads disposed within the surface mount region (10) arranged in a ring shape around the exposed pad region (30). The staggered ball pads includes first ball pads arranged in a first row (R1) and second ball pads arranged in a second row (R2). The first ball pads in the first row (R1) are arranged at two different pitches, and the second ball pads in the second row (R2) are arranged at a constant pitch. Multiple square-shaped ball pads (301-304) are arranged in a third row (R3) between the exposed pad region (30) and the staggered ball pads.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TWI853397BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TWI853397BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TWI853397BB3</originalsourceid><addsrcrecordid>eNrjZFAMLk0qLilKLElVSMxLUSjOzE1Nzs9LKS3JL1JISS3LTE7lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxIeGeFqbGxpbmTk7GRCgBAGSBJhQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Substrate and simecondutor device</title><source>esp@cenet</source><creator>TANG, HUII ; HO, SHAOUN ; LIN, HSUAN-YI ; HUANG, PU-SHAN</creator><creatorcontrib>TANG, HUII ; HO, SHAOUN ; LIN, HSUAN-YI ; HUANG, PU-SHAN</creatorcontrib><description>A board-level pad pattern includes a printed circuit board, PCB, substrate; an exposed pad region (30) disposed within a surface mount region (10) of the base substrate; and multiple staggered ball pads disposed within the surface mount region (10) arranged in a ring shape around the exposed pad region (30). The staggered ball pads includes first ball pads arranged in a first row (R1) and second ball pads arranged in a second row (R2). The first ball pads in the first row (R1) are arranged at two different pitches, and the second ball pads in the second row (R2) are arranged at a constant pitch. Multiple square-shaped ball pads (301-304) are arranged in a third row (R3) between the exposed pad region (30) and the staggered ball pads.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240821&amp;DB=EPODOC&amp;CC=TW&amp;NR=I853397B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240821&amp;DB=EPODOC&amp;CC=TW&amp;NR=I853397B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TANG, HUII</creatorcontrib><creatorcontrib>HO, SHAOUN</creatorcontrib><creatorcontrib>LIN, HSUAN-YI</creatorcontrib><creatorcontrib>HUANG, PU-SHAN</creatorcontrib><title>Substrate and simecondutor device</title><description>A board-level pad pattern includes a printed circuit board, PCB, substrate; an exposed pad region (30) disposed within a surface mount region (10) of the base substrate; and multiple staggered ball pads disposed within the surface mount region (10) arranged in a ring shape around the exposed pad region (30). The staggered ball pads includes first ball pads arranged in a first row (R1) and second ball pads arranged in a second row (R2). The first ball pads in the first row (R1) are arranged at two different pitches, and the second ball pads in the second row (R2) are arranged at a constant pitch. Multiple square-shaped ball pads (301-304) are arranged in a third row (R3) between the exposed pad region (30) and the staggered ball pads.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAMLk0qLilKLElVSMxLUSjOzE1Nzs9LKS3JL1JISS3LTE7lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxIeGeFqbGxpbmTk7GRCgBAGSBJhQ</recordid><startdate>20240821</startdate><enddate>20240821</enddate><creator>TANG, HUII</creator><creator>HO, SHAOUN</creator><creator>LIN, HSUAN-YI</creator><creator>HUANG, PU-SHAN</creator><scope>EVB</scope></search><sort><creationdate>20240821</creationdate><title>Substrate and simecondutor device</title><author>TANG, HUII ; HO, SHAOUN ; LIN, HSUAN-YI ; HUANG, PU-SHAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI853397BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>TANG, HUII</creatorcontrib><creatorcontrib>HO, SHAOUN</creatorcontrib><creatorcontrib>LIN, HSUAN-YI</creatorcontrib><creatorcontrib>HUANG, PU-SHAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TANG, HUII</au><au>HO, SHAOUN</au><au>LIN, HSUAN-YI</au><au>HUANG, PU-SHAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Substrate and simecondutor device</title><date>2024-08-21</date><risdate>2024</risdate><abstract>A board-level pad pattern includes a printed circuit board, PCB, substrate; an exposed pad region (30) disposed within a surface mount region (10) of the base substrate; and multiple staggered ball pads disposed within the surface mount region (10) arranged in a ring shape around the exposed pad region (30). The staggered ball pads includes first ball pads arranged in a first row (R1) and second ball pads arranged in a second row (R2). The first ball pads in the first row (R1) are arranged at two different pitches, and the second ball pads in the second row (R2) are arranged at a constant pitch. Multiple square-shaped ball pads (301-304) are arranged in a third row (R3) between the exposed pad region (30) and the staggered ball pads.</abstract><oa>free_for_read</oa></addata></record>
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language chi ; eng
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Substrate and simecondutor device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T13%3A10%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TANG,%20HUII&rft.date=2024-08-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETWI853397BB%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true