Semiconductor package

A semiconductor package comprising a redistribution substrate having first and second surfaces disposed opposite to each other, and including an insulation member, a plurality of redistribution layers disposed on different levels in the insulation member, and a redistribution via connecting the redistribution layers disposed on neighboring levels and having a shape narrowing from the second surface toward the first surface in a first direction. The semiconductor package further comprises a plurality of under bump metallurgy (UBM) layers, each of the plurality of UBM layers including a UBM pad disposed on the first surface of the redistribution substrate, and a UBM via connected to a redistribution layer adjacent to the first surface among the plurality of redistribution layers and connected to the UBM pad, and having a shape narrowing in a second direction opposite to the first direction. The semiconductor package further comprises at least one semiconductor chip disposed on the second surface of the redistri