SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device includes a plurality of first contacts arranged in a staircase region on one side in a second direction of a plate-like portion and along the plate-like portion, and individually connected to at least lower conductive layers among the plurality of terraced conductive layers in a first staircase portion; and a plurality of second contacts arranged in the staircase region on another side in the second direction of the plate-like portion and along the plate-like portion, and individually connected to the at least lower conductive layers in the first staircase portion, in which the plurality of first contacts is individually arranged at different positions in the second direction relative to the plate-like portion, depending on the positions in a first direction, and the plurality of second contacts is individually arranged at positions inverted in the second direction from the respective positions of the plurality of first contacts, with respect to the p