Thin-film storage transistor with ferroelectric storage layer
According to one embodiment of the present invention, a storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset relative to a ntype silicon conduction band that is less t...
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creator | CHIEN, WU-YI HENRY SAMACHISA, GEORGE HARARI, ELI PURAYATH, VINOD |
description | According to one embodiment of the present invention, a storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset relative to a ntype silicon conduction band that is less than the lowering of the tunneling barrier in the 10 tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band offset of the charge-trapping layer is selected to have a value between -1.0 eV and 2.3 eV. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TWI836349BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TWI836349BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TWI836349BB3</originalsourceid><addsrcrecordid>eNrjZLANycjM003LzMlVKC7JL0pMT1UoKUrMK84E8RTKM0syFNJSi4ryU3NSk0uKMpPhqnISK1OLeBhY0xJzilN5oTQ3g4Kba4izh25qQX58anFBYnJqXmpJfEi4p4WxmbGJpZOTMRFKABm0MP0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Thin-film storage transistor with ferroelectric storage layer</title><source>esp@cenet</source><creator>CHIEN, WU-YI HENRY ; SAMACHISA, GEORGE ; HARARI, ELI ; PURAYATH, VINOD</creator><creatorcontrib>CHIEN, WU-YI HENRY ; SAMACHISA, GEORGE ; HARARI, ELI ; PURAYATH, VINOD</creatorcontrib><description>According to one embodiment of the present invention, a storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset relative to a ntype silicon conduction band that is less than the lowering of the tunneling barrier in the 10 tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band offset of the charge-trapping layer is selected to have a value between -1.0 eV and 2.3 eV.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240321&DB=EPODOC&CC=TW&NR=I836349B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240321&DB=EPODOC&CC=TW&NR=I836349B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHIEN, WU-YI HENRY</creatorcontrib><creatorcontrib>SAMACHISA, GEORGE</creatorcontrib><creatorcontrib>HARARI, ELI</creatorcontrib><creatorcontrib>PURAYATH, VINOD</creatorcontrib><title>Thin-film storage transistor with ferroelectric storage layer</title><description>According to one embodiment of the present invention, a storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset relative to a ntype silicon conduction band that is less than the lowering of the tunneling barrier in the 10 tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band offset of the charge-trapping layer is selected to have a value between -1.0 eV and 2.3 eV.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLANycjM003LzMlVKC7JL0pMT1UoKUrMK84E8RTKM0syFNJSi4ryU3NSk0uKMpPhqnISK1OLeBhY0xJzilN5oTQ3g4Kba4izh25qQX58anFBYnJqXmpJfEi4p4WxmbGJpZOTMRFKABm0MP0</recordid><startdate>20240321</startdate><enddate>20240321</enddate><creator>CHIEN, WU-YI HENRY</creator><creator>SAMACHISA, GEORGE</creator><creator>HARARI, ELI</creator><creator>PURAYATH, VINOD</creator><scope>EVB</scope></search><sort><creationdate>20240321</creationdate><title>Thin-film storage transistor with ferroelectric storage layer</title><author>CHIEN, WU-YI HENRY ; SAMACHISA, GEORGE ; HARARI, ELI ; PURAYATH, VINOD</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI836349BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHIEN, WU-YI HENRY</creatorcontrib><creatorcontrib>SAMACHISA, GEORGE</creatorcontrib><creatorcontrib>HARARI, ELI</creatorcontrib><creatorcontrib>PURAYATH, VINOD</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHIEN, WU-YI HENRY</au><au>SAMACHISA, GEORGE</au><au>HARARI, ELI</au><au>PURAYATH, VINOD</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Thin-film storage transistor with ferroelectric storage layer</title><date>2024-03-21</date><risdate>2024</risdate><abstract>According to one embodiment of the present invention, a storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset relative to a ntype silicon conduction band that is less than the lowering of the tunneling barrier in the 10 tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band offset of the charge-trapping layer is selected to have a value between -1.0 eV and 2.3 eV.</abstract><oa>free_for_read</oa></addata></record> |
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language | chi ; eng |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
title | Thin-film storage transistor with ferroelectric storage layer |
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