Thin-film storage transistor with ferroelectric storage layer
According to one embodiment of the present invention, a storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset relative to a ntype silicon conduction band that is less t...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | According to one embodiment of the present invention, a storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset relative to a ntype silicon conduction band that is less than the lowering of the tunneling barrier in the 10 tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band offset of the charge-trapping layer is selected to have a value between -1.0 eV and 2.3 eV. |
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