Single pack & unpack network and method for variable bit width data formats for computational machines

Disclosed are methods and apparatus for bit packing data having various bit widths in a computer system. The methods and apparatus utilize a fixed bit packing or unpacking network that is configured to pack or unpack data bits of a number of different bit widths from a first number of bit locations...

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Hauptverfasser: KULKARNI, SAURABH, BAHN, JUN HO, INGLE, AJAY
Format: Patent
Sprache:chi ; eng
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Beschreibung
Zusammenfassung:Disclosed are methods and apparatus for bit packing data having various bit widths in a computer system. The methods and apparatus utilize a fixed bit packing or unpacking network that is configured to pack or unpack data bits of a number of different bit widths from a first number of bit locations to a second number of bit locations in the computer system. The network is specifically configured to pack bits stored in a same bit slot position in respective bit locations of the first number of bit locations by routing the bits into bit slots of a same bit location in the second number of bit locations to form bit bundles in respective ones of the second number of bit locations. Use of a fixed packing network affords optimal matching of bit width to an application that minimizes cost, area, and power, as well as decreasing or minimizing latency.