Metallizationlayer of an interconnct structure for a semiconductor die,method of fabricating the metallization layer,integrated circuit structure comprising the metallization layer and computing device comprising the intergrated circuit structure

Approaches for patterning metal line ends for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a metallization layer of an interconnect structure for a semiconductor die includes a metal line disposed in a trench of an interlayer dielectric (ILD) material layer. The ILD material layer is composed of a first dielectric material. A conductive via is disposed in the ILD material layer, below and electrically connected to the metal line. A dielectric plug is directly adjacent to the metal line and the conductive via. The dielectric plug is composed of a second dielectric material different from the first dielectric material.