Method of fabricating a metal-oxide-semiconductor device

Method of fabricating a metal-oxide-semiconductor device

A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA sili...

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Hauptverfasser: WANG, CHIHUNG, CHIANG, PING-HUNG, HSIUNG, CHANG-PO, WANG, CHIA-LIN, LEE, WEN-FANG, LI, NIENUNG, HSIAO, SHIH-YIN, PU, SHIHIEH, LIU, KUAN LIN
Format: Patent
Sprache:chi ; eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator WANG, CHIHUNG
CHIANG, PING-HUNG
HSIUNG, CHANG-PO
WANG, CHIA-LIN
LEE, WEN-FANG
LI, NIENUNG
HSIAO, SHIH-YIN
PU, SHIHIEH
LIU, KUAN LIN
description A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TWI681464BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TWI681464BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TWI681464BB3</originalsourceid><addsrcrecordid>eNrjZLDwTS3JyE9RyE9TSEtMKspMTizJzEtXSFTITS1JzNHNr8hMSdUtTs3NTM7PSylNLskvUkhJLctMTuVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfEh4Z5mFoYmZiZOTsZEKAEAspEuaQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of fabricating a metal-oxide-semiconductor device</title><source>esp@cenet</source><creator>WANG, CHIHUNG ; CHIANG, PING-HUNG ; HSIUNG, CHANG-PO ; WANG, CHIA-LIN ; LEE, WEN-FANG ; LI, NIENUNG ; HSIAO, SHIH-YIN ; PU, SHIHIEH ; LIU, KUAN LIN</creator><creatorcontrib>WANG, CHIHUNG ; CHIANG, PING-HUNG ; HSIUNG, CHANG-PO ; WANG, CHIA-LIN ; LEE, WEN-FANG ; LI, NIENUNG ; HSIAO, SHIH-YIN ; PU, SHIHIEH ; LIU, KUAN LIN</creatorcontrib><description>A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200101&amp;DB=EPODOC&amp;CC=TW&amp;NR=I681464B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200101&amp;DB=EPODOC&amp;CC=TW&amp;NR=I681464B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WANG, CHIHUNG</creatorcontrib><creatorcontrib>CHIANG, PING-HUNG</creatorcontrib><creatorcontrib>HSIUNG, CHANG-PO</creatorcontrib><creatorcontrib>WANG, CHIA-LIN</creatorcontrib><creatorcontrib>LEE, WEN-FANG</creatorcontrib><creatorcontrib>LI, NIENUNG</creatorcontrib><creatorcontrib>HSIAO, SHIH-YIN</creatorcontrib><creatorcontrib>PU, SHIHIEH</creatorcontrib><creatorcontrib>LIU, KUAN LIN</creatorcontrib><title>Method of fabricating a metal-oxide-semiconductor device</title><description>A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDwTS3JyE9RyE9TSEtMKspMTizJzEtXSFTITS1JzNHNr8hMSdUtTs3NTM7PSylNLskvUkhJLctMTuVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfEh4Z5mFoYmZiZOTsZEKAEAspEuaQ</recordid><startdate>20200101</startdate><enddate>20200101</enddate><creator>WANG, CHIHUNG</creator><creator>CHIANG, PING-HUNG</creator><creator>HSIUNG, CHANG-PO</creator><creator>WANG, CHIA-LIN</creator><creator>LEE, WEN-FANG</creator><creator>LI, NIENUNG</creator><creator>HSIAO, SHIH-YIN</creator><creator>PU, SHIHIEH</creator><creator>LIU, KUAN LIN</creator><scope>EVB</scope></search><sort><creationdate>20200101</creationdate><title>Method of fabricating a metal-oxide-semiconductor device</title><author>WANG, CHIHUNG ; CHIANG, PING-HUNG ; HSIUNG, CHANG-PO ; WANG, CHIA-LIN ; LEE, WEN-FANG ; LI, NIENUNG ; HSIAO, SHIH-YIN ; PU, SHIHIEH ; LIU, KUAN LIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI681464BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>WANG, CHIHUNG</creatorcontrib><creatorcontrib>CHIANG, PING-HUNG</creatorcontrib><creatorcontrib>HSIUNG, CHANG-PO</creatorcontrib><creatorcontrib>WANG, CHIA-LIN</creatorcontrib><creatorcontrib>LEE, WEN-FANG</creatorcontrib><creatorcontrib>LI, NIENUNG</creatorcontrib><creatorcontrib>HSIAO, SHIH-YIN</creatorcontrib><creatorcontrib>PU, SHIHIEH</creatorcontrib><creatorcontrib>LIU, KUAN LIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WANG, CHIHUNG</au><au>CHIANG, PING-HUNG</au><au>HSIUNG, CHANG-PO</au><au>WANG, CHIA-LIN</au><au>LEE, WEN-FANG</au><au>LI, NIENUNG</au><au>HSIAO, SHIH-YIN</au><au>PU, SHIHIEH</au><au>LIU, KUAN LIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of fabricating a metal-oxide-semiconductor device</title><date>2020-01-01</date><risdate>2020</risdate><abstract>A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method of fabricating a metal-oxide-semiconductor device
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