A placing and routing method for implementing back bias in fdsoi

The present disclosure provides a placing and routing method for implementing back bias in fully depleted silicon-on-insulator. In accordance with some illustrative embodiments herein, the placing and routing method comprises placing a first plurality of a standard tap well cell along a first direction, the standard tap well cell being formed by: routing a p-BIAS wire VPW and an n-BIAS wire VNW in a first a first metallization layer, and routing a power rail and a ground rail in a second metallization layer, the VPW and the VNW extending across each of the power and ground rail, wherein the VPWs of the first plurality of standard tap well cells are continuously connected and the VNWs of the first plurality of standard tap well cells are continuously connected.