Fuse cell circuit, fuse cell array and memory device including the same

A fuse cell circuit may include a bit line, a first fuse transistor having first and second program states, a first select transistor coupled between one terminal of the first fuse transistor and the bit line, and suitable for turning on when the first fuse transistor is selected, a second fuse transistor including one terminal coupled to the other terminal of the first fuse transistor, and having first and second program states, and a second select transistor coupled between a other terminal of the second fuse transistor and the bit line, and suitable for turning on when the second fuse transistor is selected.