Low-power, low-latency power-gate apparatus and method

A low-power, low-latency power-gate (LPLLPG) circuit is used to shut off or otherwise reduce power that is provided to electronic component(s), such as in a sleep or standby mode. ON-rush current is controlled by sizing at least one transistor in the power-gate circuit, and power consumption of the power-gate circuit in both standby state and active state is reduced by not using additional delay elements. Ramping up a gated voltage supply with low ON-rush current is performed by applying/using logic rather than delay signals. This logic does not turn ON transistors in the power-gate circuit until the gated voltage supply has ramped up close to a level of an ungated voltage supply. By not using additional delay cells, faster turn OFF of the gated voltage supply is obtained.