MEMORY SYSTEM AND SENSING DEVICE

A memory system (10) with low read power includes a first memory bank (MBA), a first path selector (YP1), a second memory bank (MBB), a second path selector (YP2), and a sensing device (100). The first path selector (YP1) is coupled to the memory cells in the first memory bank (MBA) through a plurality of first bit lines (BLA1 to BLAN). The second path selector (YP2) is coupled to the second memory cells in the second memory bank (MBB) through a plurality of second bit lines (BLB1 to BLBN). The sensing device (100) is coupled to the output terminals of the first bank selector (YP1) and the second bank selector (YP2). By sharing the sensing device (100) to sense the read currents of the corresponding memory cells, the memory system (10) is able to perform read operation with low power.