Semiconductor device

System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts a...

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Bibliographische Detailangaben
Hauptverfasser: CHANG, CHENGHUNG, HSU, YU RUNG, YEH, CHEN NAN, YU, CHEN HUA
Format: Patent
Sprache:chi ; eng
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Beschreibung
Zusammenfassung:System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.