Memory cell with reduced dibl and vss resistance

According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.