Pulse processing circuit and frequency multiplier circuit

PMOS transistors P1-Pn and PMOS transistors P1'-Pn' are respectively connected in series between a supply voltage terminal VD and output terminals OUTB, while NMOS transistors N1-Nn and NMOS transistors N1'-Nn' are respectively connected in series between the output terminals OUT...

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Bibliographische Detailangaben
1. Verfasser:	KANZAKI, MINORU
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:	PMOS transistors P1-Pn and PMOS transistors P1'-Pn' are respectively connected in series between a supply voltage terminal VD and output terminals OUTB, while NMOS transistors N1-Nn and NMOS transistors N1'-Nn' are respectively connected in series between the output terminals OUTB and a ground terminal G. Input terminals S1-Sn are respectively connected to the gates of the PMOS transistors P1'-Pn' and NMOS transistors N1-Nn, and they are respectively connected to the gates of the PMOS transistors P1-Pn and NMOS transistors N1'-Nn' through corresponding inverters IV1-IVn.