Direct memory access (DMA) controller and bus structure in a master/slave system

Direct memory access (DMA) controllers of a master/slave computer system and methods for transferring data under a DMA protocol in a master/slave system are disclosed herein. A DMA controller according to the present application comprising a first data path connected to a memory bus, wherein the memory bus is in communication with at least one memory device. The DMA controller also comprises a second data path connected to a peripheral bus, wherein the peripheral bus is in communication with at least one peripheral device. Also, the DMA controller comprises a device for transferring data between one of the at least one memory device and one of the at least one peripheral device.